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E2B0037-27-Y2
Semiconductor MSM6665C-XX
Semiconductor
This version: Nov. 1997 MSM6665C-XX Previous version: Mar. 1996
DOT MATRIX LCD CONTROLLER WITH 17-DOT COMMON DRIVER AND 80-DOT SEGMENT DRIVER
GENERAL DESCRIPTION
The MSM6665C-XX is a dot-matrix LCD control driver which has functions of displaying characters, cursor and arbitrators. The MSM6665C-XX is provided with a 17-dot common driver, 80-dot segment driver, display RAM and character ROM, and is controlled with the commands from the serial interface. The character ROM can change the font data by mask option. The MSM6665C-XX has standard ROM with 256 different character fonts. The MSM6665C-XX can drive a variety of LCD panels because the bias voltage, which determines the LCD driving voltage, can be optionally supplied from the external source.
FEATURES
* * * * * * * * * * Serial interface Contains a 17-dot common driver and an 80-dot segment driver. Contains ROM with character fonts of (5 x 7 dots) x 256. A built-in RC oscillator circuit. Provided with 80-dot arbitrators. Switchable between 1/9 duty (1 line; characters + cursor + arbitrator) and 1/17 duty (2 lines; characters + cursor, 1 line; arbitrator). Character blink operation can be switched between all-characters lighting-on mode and allcharacters lighting-off mode. SiG C-MOS process Arbitrator blink operation can be switched between 5-dot unit mode and 1-dot unit mode. Package options : 128-pin plastic QFP (QFP128-P-1420-0.50-K) (Product name: MSM6665C-XXGS-K) Aluminum pad chip (Product name: MSM6665C-XX) xx indicates code number.
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BLOCK DIAGRAM
C1 - C17 17 VDD VSS VSS1 VSS2 VSS3 VSS4 VSS5 TEST1 TEST2 TEST3 COMMON DRIVER
S1 - S80 80 SEGMENT DRIVER
LATCH
SHIFT REGISTER
RAM (512bits)
CHARACTER GENERATOR ROM (256x5x7dots)
F/F GATE 9D/ 17D RST
OSC1 OSC2 OSC3 OSC
FREQUENCY DIVIDER & TIMING GENERATION
8 SERIAL/PARALLEL INTERFACE
CS
C /D
SHT
SO
SI
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PIN CONFIGURATION (TOP VIEW)
S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 NC S45 S44 NC S43 S42 S41 S40 S39 S38 NC S37 S36 NC S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 NC TEST3 TEST2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
TEST1 OSC3 OSC2 NC OSC1 VDD SO RST 9D/17D SHT SI C/D NC CS VSS1 NC VSS2 VSS3 VSS4 VSS5 VSS (GND) C1 NC C2 C3 NC C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15
S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 C17 C16 NC
NC : No connection 128-Pin Plastic QFP
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Bias Voltage Input Voltage Power Dissipation Storage Temperature Symbol V DD VBI VI PD TSTG Condition Ta=25C, VDD-VSS Ta=25C, VDD-VSS5 Ta=25C Ta=25C QFP128-1420 *1 Rating -0.3 to +7 -0.3 to +10 -0.3 to VDD+0.3 1210 -55 to +150 Unit V V V mW C Applicable pin VDD, VSS VDD, VSS5 All inputs
*1:
The power dissipation depends on the heat sink characteristic of the package. Set a junction temperature at 150C or lower.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Bias Voltage Operating Frequency Operating Temperature Symbol VDD VBI fop Top Condition VDD-VSS VDD-VSS5 *1 -- Range 2.5 to 5.5 3 to 8 65 to 115 -40 to +85 Unit V V kHz C Applicable pin VDD, VSS VDD, VSS5 OSC1
*1:
RC oscillation, external input clock frequency
(Note) Bias voltage list
(VBI=VDD-VSS5) Symbol VDD VSS1 VSS2 VSS3 VSS4 VSS5 1/5 bias VDD VDD-1/5VBI VDD-2/5VBI VDD-3/5VBI VDD-4/5VBI VSS5 1/4 bias VDD VDD-1/4VBI VDD-2/4VBI VDD-3/4VBI VSS5 Lowest voltage Remarks Highest voltage
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ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(VDD=2.5 to 3.5V, VBI=3 to 8V, Ta=-40 to +85C) Parameter "H" Input Voltage 1 "L" Input Voltage 1 "H" Input Voltage 2 "L" Input Voltage 2 "H" Input Current 1 "L" Input Current "H" Input Current 2 "H" Output Voltage "L" Output Voltage OFF Leakage OSC "H" Output Current OSC "L" Output Current COM Output Resistance SEG Output Resistance Supply Current 1 Supply Current 2
Symbol
Condition External clock input External clock input -- -- VI=VDD VI=0V Pull-down resistance, VI=VDD IOH=-1.5mA IOL=500mA VI=VDD/0V VI=VDD-0.5V VI=0.5V I0=50mA I0=10mA RC oscillation, f=80kHz C=56pF, RS=10kW R=66kW, No load External clock, f=80kHz
Min. Typ. Max. Unit 0.8VDD -- 0 0 -- -- 0.01
VDD-0.5
Applicable pin OSC1 OSC1
Input pins except OSC1 Input pins except OSC1 Input pins except TEST
VIH1 VIL1 VIH2 VIL2 IIH1 IIL IIH2 VOH VOL IOFF IOH IOL RC RS IDD1 IDD2
VDD VDD 1 -1 0.4 -- 0.5 1 -0.15 -- 6 18 0.5 70
V V V V mA mA V V mA
-- 0.2VDD -- 0.2VDD -- -- -- -- -- -- -- -- -- -- -- --
0.8VDD --
Input pins SO SO SO
mA TEST 1 - 3
-- -- -- 0.15 -- -- -- --
mA OSC2, OSC3 mA OSC2, OSC3 kW kW mA mA C1 - C17 S1 - S80 -- --
DC Characteristics (2)
(VDD=4.5 to 5.5V, VBI=3 to 8V, Ta=-40 to +85C) Parameter "H" Input Voltage 1 "L" Input Voltage 1 "H" Input Voltage 2 "L" Input Voltage 2 "H" Input Current 1 "L" Input Current "H" Input Current 2 "H" Output Voltage "L" Output Voltage OFF Leakage OSC "H" Output Current OSC "L" Output Current COM Output Resistance SEG Output Resistance Supply Current 1 Supply Current 2
Symbol
Condition External clock input External clock input -- -- VI=VDD VI=0V Pull-down resistance, VI=VDD IOH=-1.5mA IOL=500mA VI=VDD/0V VI=VDD-0.5V VI=0.5V I0=50mA I0=10mA RC oscillation, f=80kHz C=56pF, RS=10kW R=66kW, No load External clock, f=80kHz
Min. Typ. Max. Unit 0.8VDD -- 0 0 -- -- 0.05
VDD-0.5
Applicable pin OSC1 OSC1
Input pins except OSC1 Input pins except OSC1 Input pins except TEST
VIH1 VIL1 VIH2 VIL2 IIH1 IIL IIH2 VOH VOL IOFF IOH IOL RC RS IDD1 IDD2
VDD VDD 1 -1 0.7 -- 0.5 1 -0.5 -- 6 18 1.3 100
V V V V mA mA V V mA
-- 0.2VDD -- 0.2VDD -- -- -- -- -- -- -- -- -- -- -- --
0.8VDD --
Input pins SO SO SO
mA TEST 1 - 3
-- -- -- 0.5 -- -- -- --
mA OSC2, OSC3 mA OSC2, OSC3 kW kW mA mA C1 - C17 S1 - S80 -- --
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MSM6665C-XX
(VDD=2.5 to 5.5V, Ta=-40 to +85C) Parameter CS Setup Time CS Hold Time SO ON Delay Time SO OFF Delay Time SO Output Delay Time Input Setup Time Input Hold Time Input Waveform Rise Time, Fall Time Reset Pulse Input Pulse Width Symbol tCS tCH tON tOFF tDLY tIS tIH tr, tf tRT All inputs -- CL=45pF -- -- Condition -- -- -- -- Min. 300 200 -- -- 0 200 200 -- 5 Max. -- -- 200 200 200 -- -- 100 -- s ns Unit
CS
VIH2 VIL2
t CH
VIH2 VIL2
SI
C/ D
t IS
VIH2 VIL2
t IH
VIH2 VIL2
SHT t CS "Z" t ON RST t RT
VOH VOL
"Z" t OFF
* VIH2=0.8VDD VIL2=0.2VDD VOH=VDD-0.5V VOL=0.5V
SO
t DLY
VIL2
Oscillation circuit
RS R C
OSC1 OSC2 OSC3
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Oscillation characteristics 1 (RS=10kW, C=56pF, R variable characteristics) 1/17 duty
40
VDD=3.0V VDD=5.0V
30
f=80kHz
Frame Cycle2 (ms)
Frame cycle2=27.2ms
20
10
0 55 65 75 R Resistance (kW) 85 95
Oscillation characteristics 2 (RS=10kW, R=66kW, C variable characteristics) 1/17 duty
40
VDD=3.0V VDD=5.0V
30
f=80kHz
Frame Cycle2 (ms)
Frame cycle2=27.2ms
20
10
0 35 45 55 C Capacitance (pF) 65 75
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FUNCTIONAL DESCRIPTION
Pin Functional Description * SI (Serial Input) Input pin for inputting serially commands and display data in an 8-bit unit. "H"=1 and "L"=0. When CS pin is at "H" level, read-in is executed by the leading edge of SHT. Whether input data is a command or data is determined by selecting a C/D level at the 8th leading edge of SHT. The input data is a command if C/D="H", and display data if C/D="L". * C/D (Command/Data) Input pin for determining whether input data for SI pin is a command or display data. Read-in is executed by the 8th leading edge of SHT. The input data is a command if C/ D="H", and display data if C/D="L". * SHT (Shift Clock) Clock input pin for reading-in SI input and C/D input. Read-in is executed by the clock leading edge. Read-in operation is complete with 8 clocks. Maintain this SHT pin at "H" when there is no command and data input from the SI pin. Inputting data during BUSY may cause malfunction. Valid if CS pin is at "H" level. * SO (Serial Out) Serial output pin for reading-out BUSY/NON-BUSY and display data. "H"="1" and "L"="0". If CS pin is at "H" level and Serial out Enable is set with the command, output is executed. Otherwise, this pin becomes high impedance. BUSY/NON-BUSY is output when CS pin is at "H" level. BUSY if "L" and NON-BUSY if "H". It goes BUSY after the 8th leading edge of SHT, then goes NON-BUSY automatically after a certain time. Display data is output synchronously with the leading edge of SHT. Input instruction SOE/D to set this output to Serial Out Enable or a high impedance state since the pin status is undefined after the power is applied. * CS (Chip Select) Chip Select input pin. "Chip Select ON" if CS pin is at "H" level, and "Chip Select OFF" at "L" level. When "L" level is input, SO pin becomes open and SHT pin becomes equivalent to "H" level inside of the IC. Moreover, it prevents the input rows of SI, C/D and SHT pins from current flowing. Note: For SI, C/D, SHT, SO, and CS, refer to "I/O Procedure". * RST Direct input reset input pin. By inputting "L" level pulse into RST pin, SOE/D, DISP, ABBC1/5, and ABB commands are set as D0="0". Before turning on the power, be sure to set RST pin at "L" level once. Setting this pin at "L" level during command execution may cause malfunction. * 9D/17D (1/9Duty/1/17Duty) Duty setting input pin. 1/9duty is set if this pin is at "H" level, and 1/17duty at "L" level. Choice depends on the type of panel to be used. If 1/9duty is selected, common outputs C10 to C17 should be set open.
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* TEST1, TEST2, TEST3 Test signal input pins. The manufacturer uses these pins for testing. The user should make these pins short-circuited to GND or open. * OSC1, OSC2, OSC3 Pins used for 80kHz RC oscillation circuit formation and as external master clock input pin. OSC2 and OSC3 are open during input of external master clock. See diagram below.
OSC1 10k W 625k W OSC1
80kHz
OSC2
OSC2 OPEN OSC3 OPEN
OSC3
56pF
[RC oscillation circuit formation]
[External master clock input]
< Oscillation circuit wiring diagram >
* C1 to C17, S1 to S80 (Common 1 - 17, Segment 1 - 80) LCD output pins to be connected with the LCD panel. Turning into AC is made by frame inversion. During use at 1/9duty, C1 to C9 pins are used, and C10 to C17 pins are set open. See figure below.
Arbitrator
C1 C2
Cursor
C8 C9 C10
Cursor
C16 C17
S1
S80
* VDD, VSS Supply voltage pins. VDD should be set at "H" level. VSS is a GND pin. If the battery is used, VDD is connected to the + pin, and VSS to the - pin. 9/30
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* VSS1, VSS2, VSS3, VSS4, VSS5 LCD bias voltages input pins. The voltages that are input via VDD and VSS1 to VSS5 are output for driving LCD. The LCD bias voltages are shown below.
[Case of 1/5 bias] (VBI=VDD-VSS5) Highest voltage : VDD VSS1 VSS2 VSS3 VSS4 Lowest voltage : VSS5 [Case of 1/4 bias] (VBI=VDD-VSS5) Highest voltage : VDD VSS1 VSS2, VSS3 VSS4 Lowest voltage : VSS5
(VDD-1/5 VBI) (VDD-2/5 VBI) (VDD-3/5 VBI) (VDD-4/5 VBI)
(VDD-1/4 VBI) (VDD-2/4 VBI) (VDD-3/4 VBI)
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Semiconductor List of Commands
MSM6665C-XX
X : Don't care
No. Mnemonics
1 2 3 4 5 6 LPA LOT BKCG 1/0 SOE/D DISP ABBC 1/5
Operation
Load Pointer Address Load Option Bank Change 1/0
D
7 6 5 4 3 2 1 0
Comments
1 1 1 1 1 1
1 A5 A4 A3 A2 A1 A0 Serial addresses 0 to 47 0 0 0 0 0 1 0 0 0 0 1 X X X 1 X 0 0 1 1 X 0 1 0 1 I1 I0
Meanings for I1 and I0 are set as in the table below. Valid only when 1/9duty.
0 1/0 Switching between display addresses
0 and 15, and between 16 and 31.
Serial Out Enable/Disable Display on/off Arbitrator Blink Control 1/5 dot Arbitrator Blink
1 1/0 of SO
Switching output and high impedance Display ON if D0="1"
0 1/0 Display OFF if D0="0" 0 1/0 a 5dot unit. 1dot if D0="1", 5 dot if
Sets arbitrator blink in a 1dot unit or
7
ABB
1
8 9 AINC CHB Address Increment Character Blink on/off
0
0
0
1
1
0
D0="0" Data that is input via SI after setting D0="1", is set as data for arbitrator 1/0 blink (1-dot unit). This is cancelled by D0="0"
1
0
0
X
1
X
1
X
Pointer address is incremented by 1. Controls blinking of characters and arbitrators (5-dot). Though arbitrator blink that is set as all-blank dispalyed is acceptable, blinking does not occur. Turns cursor on or off. Controls blinking of cursor. But, though blinking setting with no cursor-on setting is acceptable, blinking does not occur. CHB + CSB Sets blink patterns of characters.
0
10 11 CSC CSB Cursor Control on/off Cursor Blink on/off
X
X
X
0
0 1/0 X
0
X
X
X
0
1 1/0 X
0
X
X
X
1
0 1/0 X
12 13
CCB BPC
Character & Cursor Blink on/off Blink Pattern Control
0 1
X 0
X 0
X X
1 0
1 1/0 X 0
1 1/0 ( q :chara.) if D0="1" ( n :chara.)
if D0="0"
Notes : 1. Commands number 1 to 7 and command number 13 do not affect pointer address. 2. By entering commands number 8 to 12 or display code data, pointer address is automatically incremented by 1. 3. When Reset is entered, commands numbers 5 to 7 or number 13 are set to D0="0".
I1 0 0 1 1 I0 0 1 0 1 Operation is canceled. (No operation) Hereafter, equivalent to writing blank code at each AINC execution. Hereafter, cursor-off and blink-cancellation are executed at each AINC execution. Both of above two operations are made. Operation
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Command Description
[D7, D6, D5, D4, D3, D2, D1, D0], X=don't care * LPA (Load Pointer Address) [1,1,A5,A4,A3,A2,A1,A0] The command sets "address" data into the address pointer to specify an address on which command execution affects and an address where display data is stored. The "address" is a number between 0 and 2FH, given by A0 through A5 in hexadecimal. When addresses 30H through 3FH are specified, display data and CHB, CSC, CSB, CCB commands become invalid through an address pointer is set up. Normally, the address pointer is a loop of 0H through 2FH. * LOT (Load Option) [1,0,1,1,X,X,I1,I0] This command indicates some specific operation of display at the current address which is performed each time of AINC command execution. Operation is specified by bit I1 and I0 of the command.
I1 0 0 1 1 I0 0 1 0 1 Operation is cancelled. (No operation) Hereafter, equivalent to writing blank code at each AINC execution. Hereafter, Cursor-off and blink-cancellation are executed at each AINC execution. Both of above two operations are made. Operation
Note: When blink-cancellation is executed, all RAM data, which controls blinks for each bit of the arbitrator, go zeros. * BKCG 1/0 (Bank Change 1/0) [1,0,0,X,0,0,0,1/0] Command used to do switching between display address groups (switching between BANKs), which is valid only when 1/9duty display is selected. When D0 is "0", display address range becomes 0 through 15, and 32 through 47. When D0 is "1", display address range becomes 16 through 31, and 32 through 47. Command execution and display data setting are not affected by Bank setting. The D0 status is not changed by Reset inputting. The D0 status is unknown when the system is powered on. So D0 must be set to "0" or "1" with the command. * SOE/D (Serial Out Enable/Disable) [1,0,0,X,0,1,1,1/0] Command used to control the impedance of SO output pin. When D0 is "1", display data is output via SO pin. When D0 is "0", SO pin goes to high impedance. The D0 status is not changed by Reset inputting. The D0 status is unknown when the system is powered on. So D0 must be set to "0" or "1" with the command.
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* DISP (Display on/off) [1,0,0,X,1,0,0,1/0] Command used to control display-on and display-off of the LCD panel. When D0 is "1", the display of the LCD panel goes on, and When D0 is "0", it goes off. When the display is off, the VDD level voltage is output on all of pins of both the segment drivers and the common drivers. D0 is set to "0" after inputting Reset. * ABBC 1/5 (Arbitrator Blink Control 1/5 dot) [1,0,0,1,1,1,0,1/0] Command used to do switching between arbitrator's blinking in a 1-dot unit and or in a 5-dot unit. When D0 is "1", arbitrator's blinking comes in the 1 dot unit mode. When D0 is "0", it comes in the 5-dot unit mode. D0="0" is set after inputting Reset. Note: 1-dot unit blink setting AE See ABB. 5-dot unit blink setting AE See CHB.
* ABB (Arbitrator Blink) [1,0,0,0,1,1,0,1/0] Command used to control on/off of blinking, which is valid only when arbitrator's blinking is set in the 1-dot unit mode. Data , which are entered via SI pin after setting D0="1", are taken as arbitrator blink data (1-dot unit). Input blink data correspond to each of arbitrator's dots. When "1", blinking is on, and when "0", blinking is off. Note that the arbitrator, which arbitrator-on is not specified, is not able to blink, though blink-setting is available. Dummy data must be entered into the arbitrator blink data D5 thru D7. It is impossible to write data in addresses 00 through 31. D0="0" is set after inputting Reset. Note: If blink is set in the 5-dot unit mode, ABB command setting (D0="1" or "0") is available, but blink-on/off setting via input of display data is impossible.
* AINC (Address Increment) [1,0,0,X,1,X,1,X] Command used to increment the value of the address pointer by 1. The pointer is increment by 1 each time this command is executed. The operation set by LOT command is given to the address before being increased by 1 each time this command is execution. * CHB (Character Blink on/off)
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*
*
*
*
[0,X,X,X,0,0,1/0,X] Command used to control blinking of characters and arbitrator (5-dot unit). This command is executed to the address indicated by the address pointer. Blinking is on by setting D1="1", and off by setting D1="0". For blinking of characters, all lighting-on or all lighting-off, and characters-displaying are repeated. Choosing between all lighting-on and all lighting-off is controlled by BPC command. For arbitrator, only lighting bits repeat lighting-off and lighting-on. The blink control or arbitrator is valid only when ABBC1/5="0" and in the 5-dot unit mode. Refer to BPC. CSC (Cursor Control on/off) [0,X,X,X,0,1,1/0,X] Command used to control lighting-on and lighting-off of cursor. This command is executed to the address indicated by the address pointer.The cursor is lighting on by setting D1="1", and lighting off by setting D1="0". CSB (Cursor Blink on/off) [0,X,X,X,1,0,1/0,X] Command used to control blinking of cursor. This command is executed to the address indicated by the address pointer. Blinking is on by setting D1="1", and off by setting D1="0". The blinking in the address, where cursor-lighting-on is not specified, does not occur, though the command of blinking is acceptable. Blinking starts by specifying cursorlighting-on. CCB (Character & Cursor Blink on/off) [0,X,X,X,1,1,1/0,X] Command used to execute both CHB command and CSB command. BPC (Blink Pattern Control) [1,0,0,X,0,0,1,1/0] Command used to control blink patterns of characters. When D0="1" is set, all lighting-off (35 dots) and characters-displaying are repeated. When D0="0" is set, all lighting-on (35 dots) and characters-displaying are repeated. When D0="1" is set, if characters are blanks, their blinkings do not occur in appearance. When D0="0" is set, if characters are in all lighting-on, their blinkings do not occur in appearance. D0 is set to "0" after inputting Reset.
[D0 = "1"]
[D0 = "0"]
* Increment (+1) in address pointer When display data or arbitrator data (1-dot unit) is entered or when the following commands are executed, the address pointer is incremented by 1. AINC, CHB, CSC, CSB and CCB.
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I/O Procedure
* Input timing (command input, display data input)
8-bit input synchronization is taken by this leading edge. If input in an 8-bit unit is kept, the following leading edges of CS is not needed. CS C/ D SI SHT SO "Z" LSB MSB BUSY don't care C/D
NON-BUSY/ BUSY 17D : Max=[Master clock cycle] x 10 9D : Max=[Master clock cycle] x 20
* Output timing (display code data output) Code data or arbitrator data indicated by the address pointer is always output, provided that the SOE command has already been input.
CS C/ D SHT SO "Z"
Synchronization in an 8-bit unit. don't care
LSB MSB BUSY NON-BUSY
NON-BUSY/ BUSY 17D : Max=[Master clock cycle] x 10 9D : Max=[Master clock cycle] x 20
Note: If CS is set at "L" level when 8-bit read-out is not complete, and CS is set at "H" level again, then read-out operation is executed, uncomplete data will be output continually and the remaining read-out data will be zero.
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Various Frequency Calculation Method
* Original Clock Frequency and Blink Frequency Blink cycle calculation ([Original clock cycle] x 5) x 214 = Blink cycle ............................................. Formula 1 From formula 1, the blink frequency can be calculated. Example) When the original clock frequency is 80kHz. Clock cycle Ts=12.5[s] From formula 1, Blink cycle Tb=(12.5 x 10-6 x 5) x 214 = 1.024 [s] Thus, Blink frequency = 1 [Hz]
* Original Clock Frequency and Frame Frequency Frame cycle calculation 1/9 DUTY: (Original clock cycle) x 1152 = Frame cycle ............................. Formula 2 1/17 DUTY: (Original clock cycle) x 1088 = Frame cycle ........................... Formula 3 From Formula 2,3 the blink frequency can be calculated. Example) In the original clock 80kHz and 1/17 DUTY specifications Clock cycle Ts=12.5 [s] From formula 3, Clock cycle Tf=12.5 x 10-6 x 1088 = 13.6 [ms] Thus, Frame frequency = 73.5 [Hz]
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Display and Memory Address
Arbitrator Character 1 Display Cursor 1
Character 2 Cursor 2
32 0 RAM map 0 16 16
33 1 1 17 17
47 15 15 31 31
Arbitrator Character 1 Cursor 1 Character 2 Cursor 2
Note: Characters are entered with codes. Arbitrator is displayed with no CG ROM. The relationship between input data and display is shown below.
S5n+1
S5n+5 n : 0 - 15
D4
D0
Dummy input is required for serial data D7 through D5. Either "1" or "0" is available for data to be input into D7 through D5.
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Flowchart for Power-On Timing
Turn on power Reset input CS="H" SOE/D, D0="1" Wait for 20 clocks BPC and BKCG command set LOT, I1="1", I0="1" AINC executed 48 times LOT, I1="1", I0="1"
Input display data for initial screen
5ms required; external reset input or power-on reset input The device is enabled. Make the SO output enable, to perform busy detection. Input a wait for the SOE/D command processing. (For the processing of each command after this, perform busy detection. *1) Set the blink pattern and band change mode.
Set the Load Option. (Blank-code writing and blink-cancellation are executed each time the AINC command is executed.) Input the AINC command to clear the RAM data. Release the Load Option.
NO
Is Input of display data for initial screen completed? YES
DISP, D0="1" Normal operation
Display is turned on and the initial screen is displayed.
*1
After the required commands and display data are intered, perform busy detection based on the SO pin status. When it is confirmed that the status has been changed from BUSY (SO="L") to NON-BUSY (SO="H"), enter the next data. If busy detection is not performed, wait for 10 master oscillation clocks when used at 1/17 duty or for 20 master oscillation clocks when at 1/9 duty, then enter the next data.
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Waveforms Applied to LCD
1/17 duty (1/5 bias)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VDD VSS1 VSS2 VSS3 VSS4 VSS5 VDD VSS1 VSS2 VSS3 VSS4 VSS5
C1
C2
C17
VDD VSS1 VSS2 VSS3 VSS4 VSS5 VDD VSS1 VSS2 VSS3 VSS4 VSS5 = lighting on = lighting off
Sn
19/30
Semiconductor 1/9duty (1/4 bias)
MSM6665C-XX
123456789123456789 VDD VSS1 VSS2, 3 VSS4 VSS5 VDD VSS1 VSS2, 3 VSS4 VSS5
C1
C2
C9
VDD VSS1 VSS2, 3 VSS4 VSS5 VDD VSS1 VSS2, 3 VSS4 VSS5
Sn
= lighting on = lighting off
20/30
Semiconductor 1/17 duty (1/4 bias)
MSM6665C-XX
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VDD VSS1 VSS2, 3 VSS4 VSS5 VDD VSS1 VSS2, 3 VSS4 VSS5
C1
C2
C17
VDD VSS1 VSS2, 3 VSS4 VSS5 VDD VSS1 VSS2, 3 VSS4 VSS5
Sn
= lighting on = lighting off
21/30
Semiconductor Character Codes and Fonts of MSM6665C-02
MSM6665C-XX
00H :
08H :
10H :
18H :
20H : SP
28H : (
30H : 0
38H : 8
01H :
09H :
11H :
19H :
21H : !
29H : )
31H : 1
39H : 9
02H :
0AH :
12H :
1AH :
22H : "
2AH : *
32H : 2
3AH : :
03H :
0BH :
13H :
1BH :
23H : #
2BH : +
33H : 3
3BH : ;
04H :
0CH :
14H :
1CH :
24H : $
2CH : ,
34H : 4
3CH : <
05H :
0DH :
15H :
1DH :
25H : %
2DH : -
35H : 5
3DH : =
06H :
0EH :
16H :
1EH :
26H : &
2EH : .
36H : 6
3EH : >
07H :
0FH :
17H :
1FH :
27H : '
2FH : /
37H : 7
3FH : ?
22/30
Semiconductor
MSM6665C-XX
40H : @
48H : H
50H : P
58H : X
60H :
68H : h
70H : p
78H : x
41H : A
49H : I
51H : Q
59H : Y
61H : a
69H : i
71H : q
79H : y
42H : B
4AH : J
52H : R
5AH : Z
62H : b
6AH : j
72H : r
7AH : z
43H : C
4BH : K
53H : S
5BH : [
63H : c
6BH : k
73H : s
7BH : {
44H : D
4CH : L
54H : T
5CH : \
64H : d
6CH : l
74H : t
7CH : |
45H : E
4DH : M
55H : U
5DH : ]
65H : e
6DH : m
75H : u
7DH : }
46H : F
4EH : N
56H : V
5EH : ^
66H : f
6EH : n
76H : v
7EH : ~
47H : G
4FH : O
57H : W
5FH : _
67H : g
6FH : o
77H : w
7FH :
23/30
Semiconductor
MSM6665C-XX
24/30
Semiconductor
MSM6665C-XX
25/30
Semiconductor
MSM6665C-XX
APPLICATION CIRCUITS
Example : 1/17 duty, 1/5 bias
Cursor-contained (5 x 7 dots)16-character x 2-line LCD panel
17 dots COM C1 - C17 VDD
Bias Generation circuit
80 dots SEG S1 S80 OSC1 MSM6665C-XX OSC2 OSC3 10kW 62kW 56pF or
OSC1 OSC2 OSC3 80kHz OPEN OPEN
VSS1 VSS2 VSS3 VSS4 VSS5 9D/ 17D Vss TEST 1~3 LCD bias
RST CS C/ D SHT SO SI
PORT
26/30
Semiconductor
MSM6665C-XX
PAD CONFIGURATION
Pad Layout Chip size : 6.09 4.97mm Passivation film etched hole : 110 110mm
Y 92 93 59 58
X
117
34 1 33
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pad Name C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VSS VSS5 VSS4 VSS3 VSS2
X (m) Y (m)
-2486 -2336 -2186 -2036 -1886 -1736 -1586 -1436 -1286 -1136 -986 -836 -686 -536 -386 -227 -67 83 233 383
-2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332
Pad No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Pad Name VSS1 CS C/D SI SHT 9D/17D RST SO VDD OSC1 OSC2 OSC3 TEST1 TEST2 TEST3 S80 S79 S78 S77 S76
X (m)
Y (m)
533 683 833 983 1133 1283 1433 1583 1733 1891 2308 2489 2639 2870 2870 2870 2870 2870 2870 2870
-2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -2332 -1797 -1647 -1347 -1197 -1047 -897 -747
27/30
Semiconductor
MSM6665C-XX
Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Pad Name S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36
X (m)
Y (m)
2870 2870 2870 2870 2870 2870 2870 2870 2870 2870 2870 2870 2870 2870 2870 2870 2870 2870 2482 2332 2182 2032 1882 1732 1582 1432 1282 1132 982 832 682 532 382 232 82 -68 -218 -368 -518 -668
-597 -447 -297 -147 3 153 303 453 603 753 903 1053 1203 1353 1503 1653 1803 1953 2332 2332 2332 2332 2332 2332 2332 2332 2332 2332 2332 2332 2332 2332 2332 2332 2332 2332 2332 2332 2332 2332
Pad No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117
Pad Name S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 C17 C16
X (m)
Y (m)
-818 -968 -1118 -1268 -1418 -1568 -1718 -1868 -2018 -2168 -2318 -2468 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870 -2870
2332 2332 2332 2332 2332 2332 2332 2332 2332 2332 2332 2332 1803 1653 1503 1353 1203 1053 903 753 603 453 303 153 3 -147 -297 -447 -597 -747 -897 -1047 -1197 -1347 -1497 -1647 -1797
28/30
Semiconductor
MSM6665C-XX
Pin and Pad Correspondence The symbol for each chip pad and package pin is equal, but the numbers for each pad and pin are not equal. If both chips and packaged devices are used, the number for each chip pad should be corresponded to the number for each package pin according to each symbol listed in the table below.
Symbol C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VSS(GND) VSS5 VSS4 VSS3 VSS2 VSS1 CS C/D SI SHT 9D/17D RST SO VDD OSC1
Chip Package Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin 65 66 67 68 69 70 71 72 73 74 75 76 78 79 81 82 83 84 85 86 88 89 91 92 93 94 95 96 97 98
Symbol OSC2 OSC3 TEST1 TEST2 TEST3 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56
Chip Package Pad 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin 100 101 102 103 104 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 2
Symbol S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26
Chip Package Pad 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Pin 3 4 5 6 7 8 9 10 11 12 14 15 17 18 19 20 21 22 24 25 27 28 29 30 31 32 33 34 35 36
Symbol S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 C17 C16 - - -
Chip Package Pad 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 - - - Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 - - -
29/30
Semiconductor
MSM6665C-XX
PACKAGE DIMENSIONS
(Unit : mm) QFP128-P-1420-0.50-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.19 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 30/30

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